1. Field of the Invention
The present invention relates to a memory device, and more particularly to a memory device having a negative differential resistance device such as a tunnel diode.
2. Related Art
In a semiconductor random-access memory (hereinafter referred to as a RAM), and particularly in the case of a 1T/1C (one-transistor/one-capacitor) dynamic RAM (DRAM) made up of a plurality of cells, each of which is composed of one transistor and one capacitor element, the simplicity of the configuration of the memory is resulting in the integration levels that are currently reaching the gigabit level. In the 1T/1C DRAM, however, because the electrical charge accumulated in the capacitor element is lost at a fixed rate as a leakage current, it is necessary to perform a refreshing operation periodically, at a rate of approximately several to several tens of times per second for the capacitor element.
In a static RAM (SRAM), although refreshing is not required and the speed attained is generally higher than that of a DRAM, the fact that the SRAM requires a flip-flop circuit makes it more complex than a DRAM, it being common to configure such a memory using 6 transistors or 4 transistors and 2 polysilicon negative differential resistances, thereby resulting in a lower level of integration than the case of DRAMs.
There is therefore a desire for a memory configuration not only having the same degree of integration as DRAMs, but also not requiring a refreshing operation like SRAMs.
Such a memory configuration is disclosed, for example, in Japanese unexamined Patent Publication (KOKAI) No.10-69766, in the form of an SRAM using a resonant tunnel diode (RTD).
FIG. 8 of the accompanying drawings is a circuit diagram showing the configuration of this conventional memory cell, and FIG. 9 is a drawing illustrating the operation of the circuit of FIG. 8 in the waiting condition.
As shown in FIG. 8, the memory cell has an N-channel FET 103, the gate and the drain of which are connected to a word line 101 and a bit line 102, respectively, a cell capacitance 104 connected between the N-channel FET 103 and a cell plate CP, and the first and the second negative differential resistance devices 105 and 106, connected in series between power supply potentials VDD and VSS. The cell node SN of the negative differential resistance devices 105 and 106 is connected to the source of the N-channel FET 103.
When the memory cell is in the waiting state, that is, when the word line potential is low and the N-channel FET 43 is in the off state, the memory cell holds the content of the memory by the electrical charge stored in the cell capacitance 104. In a conventional DRAM, because of a leakage current, the amount of charge stored in the memory cell changes and information cannot be held statically. On the other hand, the series circuit formed by the negative differential resistance devices 105 and 106 has two stable operating points, shown as 111 and 112 in FIG. 9. The cell node SN voltage, therefore, is established as either one of two voltages that correspond to the two stable operating points 111 and 112, thereby enabling static holding of information.
In the conventional memory cell described above, however, in order to drive the negative differential resistance device, it is necessary to have interconnects for supplying the power supply voltage VDD and VSS for each memory cell, thereby not only increasing the surface area of the cells, but also reducing the degree of freedom possible in cell layout.
Accordingly, it is an object of the present invention to solve the problems of the prior art noted above, by providing a memory device with a small cell surface area and a high degree of freedom in cell layout.
In order to achieve the above-noted object, the present invention adopts the following basic technical constitution.
The first aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising; an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a first power supply; a first negative differential resistance element provided between the word line and the source of the FET; and a second negative differential resistance element provided between the source of the FET and a second power supply.
In the second aspect of the present invention, the FET is an N-channel FET and a potential of the second power supply is a prescribed potential greater than 0V.
In the third aspect of the present invention, the FET is a P-channel FET and a potential of the second power supply is 0V.
In the fourth aspect of the present invention, the negative differential resistance element is either an Esaki diode or a resonant tunnel diode.
The fifth aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising; an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a power supply; a first negative differential resistance element provided between the word line and the source of the FET; and a second negative differential resistance element provided between the source of the FET and the power supply.
The sixth aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising; an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a first power supply; a resistor element provided between the word line and the source of the FET; and a negative differential resistance element provided between the source of the FET and a second power supply.
The seventh aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising; an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a power supply; a resistor element provided between the word line and the source of the FET; and a negative differential resistance element provided between the source of the FET and the power supply.
The eighth aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising; an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a first power supply; a negative differential resistance element provided between the word line and the source of the FET; and a resistor element provided between the source of the FET and a second power supply.
The ninth aspect of the present invention is a memory device having a memory element provided at an intersection of a word line and a bit line, the memory element comprising; an FET, a gate of which is connected to the word line and a drain of which is connected to the bit line; a capacitor, one end of which is connected to a source of the FET and the other end of which is connected to a power supply; a negative differential resistance element provided between the word line and the source of the FET; and a resistor element provided between the source of the FET and the power supply.